Hours/Week: 40 hours/week, M-F
Start Date: ASAP
Assignment Length: 12 months
Location: Boxborough, MA
IP level functional verification
• Verification of a complex bridge IP using an equally complex SV/UVM verification environment
• Development of directed and random verification tests to validate IP/chip function
• Development and analysis of functional coverage
• Development of verification components and tools
• Regression debug
• Replicate functional issues found in external environments or post-silicon
• 5 or more years of proven verification experience on large ASIC development projects in a
hardware development setting.
• Strong background in System Verilog and UVM methodologies is a must.
• Strong debug skills and experience with debug tools such as DVE/Verdi.
• Proficient in Object Oriented programming, computer architecture and data structures.
• Knowledge of scripting languages, such as Perl or Ruby
• Strong analytical/problem solving skills and pronounced attention to details.
• Strong interpersonal and communication skills
• Must be comfortable working across geographies