This is the position of Digital Signal Processing Engineer. The incumbent will be working on the Event Horizon Telescope (EHT) is a pioneering Very Long Baseline Interferometry (VLBI) array with angular resolution of the order of ten micro-arcseconds. It operates at 1.3 mm and shorter wavelengths. The EHT investigates the characteristics of emission from Supermassive Black Holes on event-horizon scales, with the ultimate goal of making an image of emission from the near neighborhood of the black hole, thereby testing Einstein’s theory of general relativity in the strong field limit.
Current engineering work is underway to enhance the sensitivity of the EHT by increasing the bandwidth of the receivers, increasing the data rates on the back ends, and improving the throughput of the VLBI correlator. The EHT is therefore looking for a Senior Electrical Engineer with Digital Signal Processing specialization, to coordinate and play a leading role, working with senior EHT instrumental scientists, to develop next generation instrumentation for the EHT.
Will work under only the broad general direction of the Chief Electronics Engineer and Director of Central Engineering (DCE), the incumbent will work directly with the Principal Investigators and staff scientists to translate scientific requirements into pioneering technology to be applied to the development of cutting edge astronomical/astrophysical instruments in support of the advance of observatory scientific research objective, and will ensure the translation of these concepts into functional hardware.
At the GS-13 Level duties include the following:
- Contribute to the planning and implementation of an upgrade path to significantly increase the EHT’s observing sensitivity through improvements in sampled bandwidth and signal processing throughput.
- Help define the optimum architecture and technologies connecting ultra-fast (~20 giga sample-per-second) analog-to-digital converter (ADC) integrated circuit chips with commensurately fast state-of-the-art digital signal processing (DSP) processors such as FPGA’s and GPU’s.
- Work with the development team to make contributions to the detailed design, construction, testing and commissioning of a next general digital signal processing EHT platform, or building block, defined by the fully characterized ADC-DSP interfaced hardware.
- Assist with the development of Field Programmable FPGA configuration codes (“gateware”), using hardware description languages such as VHDL or Verilog, and Matlab-Simulink. This includes writing high level layers of control software in object-oriented languages such as Python and C++. Also develop digital signal processing codes for GPU processors in languages such as CUDA and OpenCL.
- Use the next generation platform as the basis for the development of the next generation EHT Digital Back End (DBE) and phased array platforms. The phased arrays are potentially to be deployed at the Submillimeter Array (SMA) in Hawaii in the first instance, and later possibly at the Atacama Large mm/Submm Array (ALMA) in Chile.
- Participate in preparation of results of technical developments for publication in professional journals and for presentation at engineering or scientific conferences and technical symposia. Contribute to review meetings covering technical and scientific research and development.
- Perform other assignments as required.
Duties at the grade 14: The incumbent will make senior contributions to the planning and implementations and play a leading role in the duties described above.
Occasional travel - May travel both domestically and internationally as necessary to support assignments and to meet colleagues.