Our client is looking of Senior Engineer - Static Timing Analysis, Synthesis, DFT. This is 6+ months contract in San Jose, CA. If you are available and interested, Please email your resume alongwith hourly rates and earliest availability.
Please let me know which one will be good match of the 2 requirements listed in below email
Position 1 – Synthesis, LEC, Physical design, place and route
Our client is looking for a Synthesis consultant with hands on experience with synthesis flow, debug, timing optimization, LEC, and DFT knowledge.
Ability to understand Verilog and System Verilog RTL constructs.
Hands on Perl and tcl scripting and a good team player.
Position 2 – Static timing analysis, Synthesis, DFT, SDC - We’re looking for DFT candidate that have strong STA/Synthesis focus on DFT’s SDC & timing modes for top level DFT.