|Job Id|| E1971950|
|Job Title||Analog IC Layout Designer|
|Company - Division||Qualcomm Atheros Inc - Qualcomm Atheros|
|Job Area||Engineering - Hardware |
|Location||Arizona - Tempe |
|Job Overview||Qualcomm is a company of inventors that unlocked 5G - ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Looking for a highly skilled Analog IC Layout designer to join our team in developing next generation Audio products.|
- Create custom layout of analog circuits in advanced nodes. Drive layout of larger subsystems and macros.
- Engage with IC design engineers to understand constraints, set floorplans and communicate issues.
- Collaborate with other layout designers across multiple geographies.
- Run full verification at block and macro levels.
- Work with CAD and Process teams to enhance/debug tools, process PDKs.
- Follow layout methodology, drive improvements.
|All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.|
- Bachelor's degree in Science, Engineering, or related field.
- 5+ years ASIC design, verification, or related work experience.
- Prefer 10+ years working experience using Cadence Virtuoso and Mentor Calibre verification tools to create custom analog layouts, specifically in layout of ADCs, DACs, high matching and low noise circuits. Need to have taken multiple designs to production.
- Recent layout experience in advanced nodes; FinFet 14nm, TSMC 22nm
- Strong written and oral communication. Able to understand key design constraints from IC design engineers to effectively execute the layout.
- Solid leadership and experience with driving contract workforce members. Experience in collaborating with teammates across multiple geographies/time zones such as UK and India.
- Excellent planning and organizational skills. Experience in providing accurate layout times for scheduling, tracking others to the plan.
- Efficient at accomplishing layouts and delivering quality work.
- Experience with the latest Cadence release (IC617) and thorough understanding of achieving VXL compliance.
- Good documentation skills.
- Strong analytical and debugging skills. Willingness to advance/improve tools, put forth new ideas to improve methodology.
- Experienced in leading top level layout, final verification, delivery of macros.
- Experienced with library manager such as Design Sync.
- Familiar with EM/IR tools, such as Totem, R3D a plus.
|Education Requirements||Required: Bachelor's, Electrical Engineering|
Preferred: Master's or PhD, Electrical Engineering