Job Title: ASIC DFT Expert
Location: remote (i.e., can work remotely from home)
Job Code: INDFT
Duration: 6 month (with possibility of extension)
- Design, implementation, and verification of scan, MBIST, on-chip scan compression, fault models, ATPG.
- Work with RTL owners to incorporate DFT logic in functional blocks.
- Simulation and verification of DFT design.
- Fault modeling and test coverage analysis.
- Post silicon validation
- Must possess a strong knowledge of ASIC DFT, scan, MBIST, on-chip scan compression, fault models, ATPG, pattern generation, and fault simulation.
- Familiar with verilog simulation.
- Ability to perform fault/test coverage analysis and improvement.
- Experience with post silicon validation.
- Knowledge in physical design flow is a big plus.
- BSEE required, MSEE preferred with 3 to 5 years of related work experience in DFT area