Experience coordinating team based design development processes for FPGA based designs is required, including mixed language VHDL/Verilog code development with proficiency in advanced VHDL grammars and techniques, simulation, verification, synthesis, timing closure and hardware based acceleration. Must have excellent verbal and written communication skills, in-depth knowledge of Xilinx Virtex MPSoCs, DDR4 physical layer, and GateRocket hardware acceleration platforms. Additionally the candidate must be able to function proficiently in an exclusively UNIX based environment with an deep in depth familiarity of UNIX based scripting, Xilinx ISE, Xilinx Vivado, Modelsim/Questa, laboratory test equipment, network test equipment, and source/revision control tools. Should be able to develop implementation architectures from requirements documents or high-level specifications with limited direction. Requires the use and maintenance of legacy IP and UNIX build environments. Requires the ability to troubleshoot designs operating within an integrated system.
Experience with terrestrial network standards, and design and debug of complex circuit boards is desired. Experience with Signal Integrity tools in support of PCB design and development is a plus.
Minimum Education Requirement: PhD plus 5 years minimum experience, or MS plus 8 years minimum experience