Vertisystem is a consulting firm in the Bay Area; we are servicing variety of companies from E commerce, Social Media, IT & Finance, Biotech, Gaming, Consumer Electronics, SAAS/ Cloud, Networking Security, Telecommunication, and Hospitality.
Title: Design Verification Engineer
Duration: 12+ Months (Extendable)
We are looking for a contractor to help the Pre-Silicon design verification team in verifying the core-level memory-subsystem blocks.
The engineer will be responsible for:
1.Developing a test bench (various components, stub model, constrained random test-generator, checkers) for verifying memory-subsystem block. This block is within the CPU core.
2.Verifying the related RTL block using this developed testbench
3.Responsible for coverage for the related block
1.(Mandatory) Candidate must have developed at leastone test-bench from scratch.
2.(Mandatory) Candidate must have a solid understanding and hands on experience withSystem Verilog, uvm, Verilog.
3.(Highly desirable) Candidate must have worked on verifying one of the following blocks Level 2 Cache, Load/Store Unit, Data Cache Unit.
4.Candidate should have a good understanding of howCPUcore works.
5.Maximum 7 Years of experience
All your information will be kept confidential according to EEO guidelines.